| 发明名称 |
WEAK KEEPER CIRCUIT FOR MEMORY DEVICE |
| 摘要 |
A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p- channel metal-oxide-silicon (PMOS) transistor. |
| 申请公布号 |
US2014226418(A1) |
申请公布日期 |
2014.08.14 |
| 申请号 |
US201313765533 |
申请日期 |
2013.02.12 |
| 申请人 |
QUALCOMM INCORPORATED |
发明人 |
Ganesan Balachander;Chaba Ritu;Yoon Sei Seung |
| 分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory circuit, comprising:
a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells; a sense inverter coupled to an output of the bit line; and a keeper circuit having an output coupled to the bit line to compensate for current leakage from the plurality of bit cells, the keeper circuit comprising an n- channel metal-oxide-silicon (NMOS) transistor in series with a p-channel metal-oxide- silicon (PMOS) transistor. |
| 地址 |
San Diego CA US |
