发明名称 FUNCTIONAL MATERIAL SYSTEMS AND PROCESSES FOR PACKAGE-LEVEL INTERCONNECTS
摘要 Interconnect packaging technology for direct-chip-attach, package-on-package, or first level and second level interconnect stack-ups with reduced Z-heights relative to ball technology. In embodiments, single or multi-layered interconnect structures are deposited in a manner that permits either or both of the electrical and mechanical properties of specific interconnects within a package to be tailored, for example based on function. Functional package interconnects may vary one of more of at least material layer composition, layer thickness, number of layers, or a number of materials to achieve a particular function, for example based on an application of the component(s) interconnected or an application of the assembly as a whole. In embodiments, parameters of the multi-layered laminated structures are varied dependent on the interconnect location within an area of a substrate, for example with structures having higher ductility at interconnect locations subject to higher stress.
申请公布号 US2014225265(A1) 申请公布日期 2014.08.14
申请号 US201213976192 申请日期 2012.03.29
申请人 Sidhu Rajen S.;Dadi Ashay A.;Dudek Martha A. 发明人 Sidhu Rajen S.;Dadi Ashay A.;Dudek Martha A.
分类号 H01L23/532;H01L21/768 主分类号 H01L23/532
代理机构 代理人
主权项 1. An integrated electronic device, comprising: a first substrate with top level interconnect pads and a dielectric material disposed between the pads; and a first multi-layered interconnect stack disposed over a first top level interconnect pad and electrically coupled to the pad, wherein the first multi-layered interconnect stack forms a protrusion extending from the dielectric material a distance sufficient to make first contact with a second substrate, and wherein the first multi-layered interconnect stack comprises layers of at least two distinct materials that are reflowable into a composite interconnect joint.
地址 Chandler AZ US