Multi-serial interface stacked-die memory architecture

摘要

Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.

主权项

1. A memory system comprising:
a memory vault; a memory vault controller configured to communicate with the memory vault; a communication link interface configured to communicatively couple the memory vault controller at least one of an originating device or a destination device; a switch configured to connect the communication link interface to the memory vault controller; a packet decoder coupled to the switch to receive an outbound packet sent from the originating device across an outbound of the communication link interface, to extract at least one of an outbound memory command, an outbound memory address, or an outbound memory data field from the outbound packet, and to present a set of select signals to the switch; and a packet encoder coupled to the switch to receive at least one of an inbound memory command, an inbound memory address, or inbound memory data from the memory vault controller, and to encode the inbound memory address or the inbound memory data into an inbound packet for transmission across an inbound of the communication link interface to the destination device, wherein the communication link interface includes:
a differential pair serial path coupled to the originating device;a deserializer coupled to the differential pair serial path; anda demultiplexer communicatively coupled to the deserializer.