Multiple clocking modes for a CCD imager

摘要

A CCD image sensor includes vertical CCD shift registers and gate electrodes disposed over the vertical CCD shift registers. The gate electrodes are divided into distinct groups of gate electrodes. The CCD image sensor is adapted to operate in an accumulation mode and a charge transfer mode, an accumulation mode and a charge shifting mode, or an accumulation mode, a charge transfer mode, and a charge shifting mode. The charge transfer mode has an initial charge transfer phase and a final charge transfer phase. The charge shifting mode has an initial charge shifting phase and a final charge shifting phase.

主权项

1. A method for operating a charge-coupled device (CCD) image sensor including a plurality of vertical CCD shift registers and a plurality of gate electrodes disposed over the vertical CCD shift registers, wherein the plurality of gate electrodes are divided into distinct groups of gate electrodes, the method comprising:
applying, at a first time step, an accumulation clock signal having a first voltage level to all of the gate electrodes disposed over the vertical CCD shift registers for accumulating minority charge carriers; applying, at a second time step, a depletion clock signal having a different second voltage level to a respective one of the gate electrodes in each distinct group of gate electrodes while substantially simultaneously applying a compensation clock signal having a different third voltage level to all of the remaining gate electrodes in each distinct group of gate electrodes, wherein a difference between the first voltage level and the second voltage level applied to the respective one of the gate electrodes is compensated by a collective voltage difference between the first voltage level and the third voltage level applied to the remaining gate electrodes in each distinct repeating group of gate electrodes; and applying, at a third time step, the depletion clock signal having the second voltage level to another respective one of the gate electrodes in each distinct group of gate electrodes while substantially simultaneously applying the compensation clock signal having the third voltage level to the respective one of the gate electrodes clocked by the depletion clock signal at the second time step in each distinct group of gate electrodes, wherein a difference between the third voltage level and the second voltage level applied to the another respective one of the gate electrodes is compensated by a difference between the second voltage level and the third voltage level applied to the previous respective one of the gate electrodes.