Array substrate for fringe field switching mode liquid crystal display device and method of manufacturing the same

摘要

A method of manufacturing an array substrate for an FFS mode LCD device includes forming a gate line and a gate electrode on a substrate, forming a pixel electrode in the pixel region, forming a gate insulating layer on the gate line, the gate electrode and the pixel electrode, forming a data line, a source electrode, a drain electrode, and a semiconductor layer on the gate insulating layer, forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer including a drain contact hole and a pixel contact hole, and forming a connection pattern and a common electrode on the passivation layer, wherein the common electrode includes bar-shaped first openings in the pixel region, and the connection pattern contacts the drain electrode and the pixel electrode through the drain contact hole and the pixel contact hole, respectively.

主权项

1. A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device, comprising:
forming a gate line and a gate electrode on a substrate comprising a pixel region defined thereon; forming a transparent pixel electrode in the pixel region directly on and contacting the substrate; forming a gate insulating layer on the gate line, the gate electrode and the transparent pixel electrode, the gate insulating layer covering top and side surfaces of the transparent pixel electrode; forming a data line, a source electrode, a drain electrode, and a semiconductor layer on the gate insulating layer, the data line crossing the gate line to define the pixel region, the semiconductor layer disposed over the gate electrode, the source electrode and the drain electrode spaced apart from each other over the semiconductor layer; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer comprising a drain contact hole and a pixel contact hole; and forming a connection pattern and a common electrode on the passivation layer, wherein the common electrode comprises bar-shaped first openings in the pixel region, (ii) a second opening corresponding to the semiconductor layer and exposing a top surface of the passivation layer, and (iii) a third opening corresponding to the data line, and the connection pattern contacts the drain electrode and the transparent pixel electrode through the drain contact hole and the pixel contact hole, respectively.