Delay compensation in equalizer-based receiver

摘要

A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.

主权项

1. A multi-stage receiver having a sequence of processing stages, at least one processing stage comprising:
a first processing block adapted to receive an input signal and generate from the input signal one or more processing parameters; a delay controller adapted to generate a delay value based on either a receiver input signal or a processed version of the receiver input signal; a delay block adapted to generate a delayed signal from an original signal based on the delay value; and a second processing block adapted to apply the one or more processing parameters to the delayed signal to generate an output signal, wherein:
the delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block, andthe delay controller is adapted to select the delay value for the delay block by calculating a processing delay associated with the generation of the one or more processing parameters by the first processing block.