Serializer-deserializer clock and data recovery gain adjustment

摘要

In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve.

主权项

1. Apparatus for a voltage-controlled oscillator based clock and data recovery circuit, the apparatus comprising:
a phase detector for comparing the phase of feedback signal and an input signal and providing a phase difference signal between the input signal and the feedback signal; a voltage controlled oscillator responsive to a first control signal and a second control signal received at a respective first control input node and a respective second control input node and generating an output signal, wherein the output signal is divided to multiple phase signals by a programmable divider, and one of the multiple phase signals is coupled to the phase detector as the feedback signal; a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, wherein another one of the multiple phase signals is sent to the frequency calibration module as a calibrating reference frequency that is compared to a reference clock frequency from a reference clock over a period of time; a gear shifting control module configured to generate gear shifting control signals according to a programmed variable gain, the gear shifting control module controlling a gain change of the first and second control signals in time, wherein the gear shifting control signals are combined with the phase difference signal in control multipliers to provide the first and second control signals for the voltage-controlled oscillator, and wherein the second control signal is provided by integrating the first control signal; and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting up or down, and adjusts a voltage-controlled oscillator gain, and adjusting an overall clock and data recovery gain over a voltage-controlled oscillator control curve.