Gate-Length Biasing for Digital Circuit Optimization

摘要

Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology that changes a nominal gate-length of a transistor to a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length.

主权项

1. A gate-length biasing method for modifying a nominal cell for an integrated digital circuit, the nominal cell containing one or more transistors, the method comprising:
(a) selecting a trial set of one or more transistors in the nominal cell, each selected transistor having a nominal gate-length, the one or more transistors having gate widths defined as part of the nominal cell; (b) determining small bias lengths for the selected trial set of transistors, the small bias lengths all less than a predefined fraction of the nominal gate-length; (c) adjusting the gate-lengths of the selected trial set of transistors by the small bias lengths to create a trial biased cell; (d) comparing the trial biased cell to a current best biased cell with respect to a predefined goal including a tradeoff between reducing a leakage power and reducing an impact on timing delays for the integrated digital circuit; and (e) updating the current best biased cell based on the comparison; wherein gate-length biasing is not width-sizing of the gate widths; wherein gate-length biasing is performed on the one or more transistors of the nominal cell post layout, for the integrated digital circuit.