SYSTEM AND DETERMINISTIC METHOD FOR SERVICING MSI INTERRUPTS USING DIRECT CACHE ACCESS

摘要

A system and method for creating a guaranteed MSI latency by coupling a coprocessor, which may be a dedicated agent, to the existing front side bus (“FSB”) in a processor (e.g., Intel® Atom™ processor) to handle deterministic interrupts. MSI interrupts may be automatically forwarded to the coprocessor using the existing Direct;Cache Access field. Users may control the handling time and methodology of MSI interrupts.

主权项

1. A system for servicing message signaled interrupts (“MSI”), comprising:
a first processor bus coupled to a microcontroller hub (MCH); a first processing core coupled to the first processor bus; and a first external coprocessor coupled to the first processor bus; wherein the first external coprocessor is a dedicated agent for handling MSIs.