发明名称 SYSTEM AND METHOD FOR PER-TASK MEMORY PROTECTION FOR A NON-PROGRAMMABLE BUS MASTER
摘要 A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task.
申请公布号 US2014223047(A1) 申请公布日期 2014.08.07
申请号 US201314015561 申请日期 2013.08.30
申请人 TEXAS INSTRUMENTS INCORPORATION 发明人 CHAVALI Balatripura Sodemma;GREB Karl Friedrich;SUVARNA Rajeev
分类号 G06F13/28;G06F13/40 主分类号 G06F13/28
代理机构 代理人
主权项 1. A system, comprising: a non-programmable bus master, comprising: a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions; andhardware logic to: execute a first task and a second task, wherein the tasks generate transactions and wherein the hardware logic switches between executing the first and second tasks;cause the MPU to operate in the first configuration when the hardware logic executes the first task; andcause the MPU to operate in the second configuration when the hardware logic executes the second task.
地址 Dallas TX US