发明名称 INTEGRATED CIRCUIT
摘要 Object An objective is to provide an integrated circuit capable of performing an operation check test for a combination circuit present in sections that are not connected by a scan chain. Solution Means An integrated circuit includes a first signal processing circuit in which a plurality of first combination circuits and a plurality of scan FFs (Flip Flop) are connected in an order of a scan FF, a first combination circuit, and a scan FF; a second signal processing circuit including a second combination circuit different from the first combination circuit; a first selection circuit configured to select data from a scan FF on an input side of one of the plurality of first combination circuits or data from an input terminal of the second signal processing circuit, and to output the selected data to the second combination circuit; and a second selection circuit configured to select data from another one of the plurality of first combination circuits different from the one of the plurality of first combination circuits or data from the second combination circuit, and to output the selected data to the scan FF on an output side of the another one of the plurality of first combination circuits.
申请公布号 EP2624000(A4) 申请公布日期 2014.08.06
申请号 EP20100857801 申请日期 2010.09.27
申请人 FUJITSU LIMITED 发明人 ITOZAWA, SHINTARO;NISHIO, MASAHIRO;NAKAYAMA, HIROSHI;ICHIMIYA, JUNJI;TAKAHASHI, JIN
分类号 G01R31/28;G01R31/3185;H01L21/822;H01L27/04 主分类号 G01R31/28
代理机构 代理人
主权项
地址