Semiconductor device

摘要

A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

主权项

1. A semiconductor device comprising:
a plurality of word lines extending in a first direction; a plurality of bit line pairs extending in a second direction intersecting the first direction; a plurality of memory cells arranged at crossing portions of the word lines and the bit line pair, and configured with a circuit including a first MIS transistor; a sense amplifier circuit operable to amplify a signal read from one of the memory cells through one of the bit line pair, in response to an enable signal; a control circuit operable to generate a first signal in response to an access instruction to the memory cells; and a timing adjusting circuit operable to receive the first signal inputted and to generate a second signal serving as an origin of the enable signal, by delaying the first signal, wherein the timing adjusting circuit comprises: a first wiring arranged collaterally with the bit line pair and operable to receive the first signal transmitted at one end and to output the second signal from the other end; and a load circuit including a plurality of second MIS transistors coupled to the first wiring.