High speed RF divider

摘要

High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

主权项

1. A Radio Frequency (RF) quadrature clock divider comprising:
positive and negative differential RF clock inputs; four clocked inverter stages connected in a serial ring formation, each clocked inverter stage comprising a pair of stacked PMOS transistors connected to a pair of stacked NMOS transistors; and an inverter interposed between each clocked inverter stage; wherein one of the PMOS transistors of each clocked inverter stage is connected to a positive voltage supply node and one of the NMOS transistors is connected to a ground node; wherein the gates of one PMOS transistor and one NMOS transistor of each clocked inverter stage are connected together to form an inverter; and wherein the gate of one PMOS transistor and one NMOS transistor of each clocked inverter stage are each connected to a different input clock, such that the positive and negative inputs to the PMOS and NMOS transistors alternate at each successive clocked inverter circuit in the ring.