发明名称 Amorphous oxide semiconductor thin film transistor fabrication method
摘要 This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.
申请公布号 US8797303(B2) 申请公布日期 2014.08.05
申请号 US201113052446 申请日期 2011.03.21
申请人 QUALCOMM MEMS Technologies, Inc. 发明人 Kim Cheonhong;Hong John Hyunchul;Pan Yaoling
分类号 G09G5/00;H01L29/10;H01L29/786;H01L29/66;G02B26/00 主分类号 G09G5/00
代理机构 Weaver Austin Villeneuve & Sampson LLP 代理人 Weaver Austin Villeneuve & Sampson LLP
主权项 1. An apparatus comprising a thin film transistor (TFT), the TFT comprising: a substrate including a surface; an oxide semiconductor layer disposed over the substrate surface, a channel region of the oxide semiconductor layer being between a source region and a drain region of the oxide semiconductor layer, the source region and the drain region of the oxide semiconductor layer being a heavily doped n-type oxide semiconductor; a gate dielectric on the channel region of the oxide semiconductor layer; a gate metal on the gate dielectric, wherein the gate metal defines the channel region of the oxide semiconductor layer; a source metal oxide on the source region and a drain metal oxide on the drain region of the oxide semiconductor layer, wherein the source metal oxide defines the source region and the drain metal oxide defines the drain region of the oxide semiconductor layer; a passivation dielectric on the gate metal and on the source metal oxide and the drain metal oxide; a first metal contact extending through the source metal oxide and contacting the source region of the oxide semiconductor layer; and a second metal contact extending through the drain metal oxide and contacting the drain region of the oxide semiconductor layer.
地址 San Diego CA US