| 发明名称 | Low-power high-resolution time-to-digital converter | ||
| 摘要 | Disclosed is a low-power and high-resolution time-to-digital converter including: a coarse delay cell configured to delay a reference clock by a coarse delay time and output the reference clock; a rising-edge retimer configured to output a rising-edge retimed clock synchronized with the rising-edge of a DCO clock in response to the reference clock; a falling-edge retimer configured to output a falling-edge retimed clock synchronized with the falling-edge of the DCO clock; a first sampler configured to latches output of the coarse delay cell in response to the rising-edge retimed clock and the falling-edge retimed clock; and a pseudo-thermometer code edge detector configured to detect a rising-edge fractional phase error between the reference clock and the rising-edge retimed clock as a coarse phase error from a signal output by the first sampler, and detect a falling-edge fractional phase error between the reference clock and the falling-edge retimed clock. | ||
| 申请公布号 | US8797203(B2) | 申请公布日期 | 2014.08.05 |
| 申请号 | US201313743711 | 申请日期 | 2013.01.17 |
| 申请人 | Electronics and Telecommunications Research Institute | 发明人 | Lee Ja Yol |
| 分类号 | H03M1/50 | 主分类号 | H03M1/50 |
| 代理机构 | Rabin & Berdo, P.C. | 代理人 | Rabin & Berdo, P.C. |
| 主权项 | 1. A low-power high-resolution time-to-digital converter comprising: a coarse delay cell configured to delay a reference clock by a coarse delay time and output the reference clock; a rising-edge retimer configured to output a rising-edge retimed clock synchronized with the rising-edge of a DCO (Digitally Controlled Oscillator) clock in response to the reference clock; a falling-edge retimer configured to output a falling-edge retimed clock synchronized with the falling-edge of the DCO clock in response to the reference clock; a first sampler configured to latch output of the coarse delay cell in response to the rising-edge retimed clock and the falling-edge retimed clock; and a pseudo-thermometer code edge detector configured to detect a rising-edge fractional phase error between the reference clock and the rising-edge retimed clock as a coarse phase error from a signal output by the first sampler, and detect a falling-edge fractional phase error between the reference clock and the falling-edge retimed clock. | ||
| 地址 | Daejeon KR | ||