发明名称 Low-Pin-Count Non-Volatile Memory Embedded in a Integrated Circuit without any Additional Pins for Access
摘要 A low-pin-count non-volatile memory (NVM) embedded an integrated circuit can be accessed without any additional pins. The NVM has one or more memory cells and at least one of the NVM cells can have at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector can be coupled to a second supply voltage line and has a selecting signal. The integrated circuit can include at least one test mode detection circuit to activate a test mode upon detecting an abnormal (or out of normal) operation condition(s). Once a test mode is activated, at least one I/O or supply voltage of the integrated circuit can be used as the I/O or supply voltage of the NVM to select at least one NVM cell for read, program into nonvolatile, or volatile state. At least one NVM cell can be read during ramping of at least one supply voltage line.
申请公布号 US2014211567(A1) 申请公布日期 2014.07.31
申请号 US201414231413 申请日期 2014.03.31
申请人 Chung Shine C. 发明人 Chung Shine C.
分类号 G11C7/10;G11C16/10;G11C29/02;G11C17/00 主分类号 G11C7/10
代理机构 代理人
主权项 1. A low-pin-count non-volatile memory (NVM) integrated in an integrated circuit, the NVM having a test mode, the NVM comprising: one or more NVM cells; at least one of the NVM cells including at least: an NVM element coupled to a first supply voltage line; anda selector coupled to the NVM element and a second supply voltage line having a select signal; and at least one test mode detection circuit to detect abnormal operational conditions and to activate a test mode based on the detected abnormal operational conditions, wherein at least one I/O or supply voltage pins of the integrated circuit is configured to be used as the I/O or supply voltage of the NVM to generate at least one select signal to select at least one NVM cells after the test mode is activated.
地址 San Jose CA US