| 发明名称 |
PHASE INTERPOLATION CIRCUIT AND RECEIVER CIRCUIT |
| 摘要 |
A phase interpolation circuit includes: a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and combining weighed first reference signals; a second circuit configured to generate a second intermediate signal by weighing second reference signals having phases different from the phases of the first reference signals by a certain value with a second ratio equal to the first ratio and combining weighted second reference signals; and a third circuit configured to generate an output signal by combining the first intermediate signal and the second intermediate signal. |
| 申请公布号 |
US2014211898(A1) |
申请公布日期 |
2014.07.31 |
| 申请号 |
US201314144075 |
申请日期 |
2013.12.30 |
| 申请人 |
FUJITSU SEMICONDUCTOR LIMITED |
发明人 |
KATOH Toshie |
| 分类号 |
H04L7/00;H03H11/20;H04B1/16 |
主分类号 |
H04L7/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A phase interpolation circuit comprising:
a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and combining weighed first reference signals; a second circuit configured to generate a second intermediate signal by weighing second reference signals having phases different from the phases of the first reference signals by a certain value with a second ratio equal to the first ratio and combining weighted second reference signals; and a third circuit configured to generate an output signal by combining the first intermediate signal and the second intermediate signal. |
| 地址 |
Yokohama JP |
