Persistent Relocatable Reset Vector for Processor

摘要

In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time.

主权项

1. An apparatus comprising:
a processor including a reset vector base address register, wherein the processor is configured to update the reset vector base address register with a reset vector address provided on an input to the processor, wherein the processor is configured to update the reset vector base address register responsive to a reset of the processor, and wherein the processor is configured to initiate instruction fetching responsive to the reset vector address in the reset vector base address register and responsive to being released from reset; and a logic circuit that remains powered on if the apparatus is powered on, wherein the processor is configured to be powered down intermittently while the apparatus is powered on, wherein the logic circuit includes a second register, wherein the second register is coupled to the input to the processor to supply the reset vector address to the reset vector base address register, and wherein the second register is memory-mapped to permit update by instructions executable by the processor.