Digital Circuit Verification Monitor

摘要

A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

主权项

1. A method for providing information relating to a verification of a digital circuit by using a computer, wherein the verification comprises verifying that an assignment (s) is observation covered by a proven property (p) for a representation (D) of the digital circuit, the assignment (s) having a first side (1) and a second side (r), the method comprising:
a) replacing said second side (r) of the assignment (s) with a first free variable (v); b) checking for the presence of a counter-example (c); and c) indicating, by using said computer, that a first input value (s1) is covered when a counter-example (c1) is found and that the first input value (s1) is uncovered when a counter-example (c1) is not found.