发明名称 Integrated Circuit Within Semiconductor Chip Including Cross-Coupled Transistor Configuration
摘要 A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and a conductive interconnect structure.
申请公布号 US2014210015(A1) 申请公布日期 2014.07.31
申请号 US201414242308 申请日期 2014.04.01
申请人 Tela Innovations, Inc. 发明人 Becker Scott T.;Mali Jim;Lambert Carole
分类号 H01L27/092;G06F17/50 主分类号 H01L27/092
代理机构 代理人
主权项 1. An integrated circuit within a semiconductor chip, comprising: a first transistor of a first transistor type having a gate electrode, a first diffusion terminal of a first diffusion type, and a second diffusion terminal of the first diffusion type; a second transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type; a third transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type; a fourth transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type; a first transistor of a second transistor type having a gate electrode, a first diffusion terminal of a second diffusion type, and a second diffusion terminal of the second diffusion type; a second transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type; a third transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type; a fourth transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type, both the gate electrode of the first transistor of the first transistor type and the gate electrode of the first transistor of the second transistor type formed by a first linear-shaped conductive structure, the gate electrode of the first transistor of the first transistor type electrically connected to the gate electrode of the first transistor of the second transistor type through the first linear-shaped conductive structure, the gate electrode of the second transistor of the first transistor type formed by a second linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the second linear-shaped conductive structure is of the first transistor type, the gate electrode of the second transistor of the second transistor type formed by a third linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the third linear-shaped conductive structure is of the second transistor type, the first, second, and third linear-shaped conductive structures oriented to extend lengthwise in a first direction, the first linear-shaped conductive structure positioned between the second and third linear-shaped conductive structures in a second direction perpendicular to the first direction, the first, second, third, and fourth transistors of the first transistor type forming a first collection of transistors, the first, second, third, and fourth transistors of the second transistor type forming a second collection of transistors, the first collection of transistors separated from the second collection of transistors by an inner region that does not include a source or a drain of any transistor, the first and second transistors of the first transistor type positioned adjacent to each other, the first diffusion terminal of the first transistor of the first transistor type electrically and physically connected to the first diffusion terminal of the second transistor of the first transistor type, the first diffusion terminal of the first transistor of the first transistor type also electrically connected to a common node, the first diffusion terminal of the second transistor of the first transistor type also electrically connected to the common node, the first and second transistors of the second transistor type positioned adjacent to each other, the first diffusion terminal of the first transistor of the second transistor type electrically and physically connected to the first diffusion terminal of the second transistor of the second transistor type, the first diffusion terminal of the first transistor of the second transistor type also electrically connected to the common node, the first diffusion terminal of the second transistor of the second transistor type also electrically connected to the common node, the first diffusion terminal of the third transistor of the first transistor type electrically connected to the second diffusion terminal of the first transistor of the first transistor type, the first diffusion terminal of the fourth transistor of the first transistor type electrically connected to the second diffusion terminal of the second transistor of the first transistor type, the first diffusion terminal of the third transistor of the second transistor type electrically connected to the second diffusion terminal of the first transistor of the second transistor type, the first diffusion terminal of the fourth transistor of the second transistor type electrically connected to the second diffusion terminal of the second transistor of the second transistor type, the gate electrode of the third transistor of the first transistor type electrically connected to the gate electrode of the fourth transistor of the second transistor type, the gate electrode of the third transistor of the second transistor type electrically connected to the gate electrode of the fourth transistor of the first transistor type; a first interconnect conductive structure located within a first interconnect chip level of the semiconductor chip, the first interconnect chip level formed above a level of the semiconductor chip that includes the first, second, and third linear-shaped conductive structures; a second interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the second interconnect conductive structure physically separate from the first interconnect conductive structure; a first gate contact in contact with the first linear-shaped conductive structure, the first gate contact formed to extend in a vertical direction substantially perpendicular to a substrate of the semiconductor chip from the first linear-shaped conductive structure through a dielectric material to contact the second interconnect conductive structure; a second gate contact in contact with the second linear-shaped conductive structure, the second gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the second linear-shaped conductive structure through the dielectric material to contact the first interconnect conductive structure; a third gate contact in contact with the third linear-shaped conductive structure, the third gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the third linear-shaped conductive structure through the dielectric material to contact the first interconnect conductive structure, wherein the first interconnect conductive structure is physically separate from the first gate contact, and wherein the second interconnect conductive structure is physically separate from the second and third gate contacts, the integrated circuit being part of a digital logic circuit.
地址 Los Gatos CA US