发明名称 Coding method and device for Quasi-Cyclic LDPC codes
摘要 <p>An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m-r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k 1 , k 2 , ..., k r ; a first arithmetic operation for performing polynomial multiplication on the (m-r) pieces of first blocks, and outputting r pieces of bit sequences having a length n; and a second arithmetic operation for performing a polynomial division and a polynomial multiplication on the r pieces of second blocks and r pieces of operation results of the first arithmetic operation, and outputting a bit sequence including redundant bit sequences having respective lengths n-k 1 , n-k 2 , ..., n-k r .</p>
申请公布号 EP2031759(B1) 申请公布日期 2014.07.30
申请号 EP20070742407 申请日期 2007.04.25
申请人 NEC CORPORATION 发明人 KAMIYA, NORIFUMI
分类号 H03M13/11;G11B20/18;H03M13/47 主分类号 H03M13/11
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