Accelerating memory operations using virtualization information

摘要

A method of accelerating memory operations using virtualization information includes executing a hypervisor on hardware resources of a computing system. A plurality of domains are created under the control of the hypervisor. Each domain is allocated memory resources that include accessible memory space that is exclusively accessible by that domain. Each domain is allocated one or more processor resources. The hypervisor identifies domain layout information that includes a boundary of accessible memory space of each domain. The hypervisor provides the domain layout information to each processor resource. Each processor resource is configured to implement, on a per domain basis, a restricted coherency protocol based on the domain layout information. The restricted coherency protocol bypasses, relative to the domain, downstream caches when a cache line falls within the accessible memory space of that domain.

主权项

1. A method of accelerating memory operations using virtualization information comprising:
executing a hypervisor on hardware resources of a computing system; creating a plurality of domains under the control of the hypervisor; allocating to each domain memory resources comprising accessible memory space that is exclusively accessible by that domain; allocating to each domain one or more processor resources; identifying domain layout information comprising a boundary of accessible memory space of each domain; providing the domain layout information to each processor resource; configuring, by the hypervisor, each processor resource through a hyperprivileged register; and configuring each processor resource to implement, on a per domain basis, a restricted coherency protocol based on the domain layout information, wherein the restricted coherency protocol bypasses, relative to the domain, downstream caches when a cache line falls within the accessible memory space of that domain, and wherein the hyperprivileged register configures the coherency regions based upon whether the processor resource of the domain consists of a single hardware thread, a single core, multiple cores, or multiple processors.