| 主权项 |
1. A memory control system connected to a plurality of memories, the memory control system comprising:
a plurality of I/O circuits; and a monitoring circuit that monitors usage states of the memories, wherein each of the I/O circuits is connected t one of the memories, when one of the memories is accessed, each of the I/O circuits that is connected thereto is used, the I/O circuit consumes power to operate, and the monitoring circuit determines, among the memories, a memory to which access is permitted, based on the usage states of the memories, the memory control system further comprising a power control circuit that performs, when a predetermined condition for the usage states of the memories is satisfied, and an unused memory is present among the memories, a power consumption reduction process for causing a target I/O circuit to consume less power than an other one of the I/O circuits, the target I/O circuit being an I/O circuit among the I/O circuits that is connected to the unused memory, wherein the memories are set to have an n number of segments, n being an integer greater than or equal to 2, each of the n number of the segments corresponds to all or part of a plurality of regions identified by the same address for the memories, and the memories are accessed on a segment basis, the memory control system further comprising a memory management circuit that (a) makes, every time an instruction to perform an access process for accessing one of the n number of the segments is received, the segment to be accessed valid and (b) makes, every time a predetermined process for causing the access process at least once is completed, the segment to be accessed invalid, wherein the monitoring circuit determines, among the memories, the memory to which access is permitted, based on the number of valid segments among the n number of the segments. |
