| 发明名称 |
MEMORY ACCESS METHODS AND APPARATUS |
| 摘要 |
A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline. |
| 申请公布号 |
US2014208156(A1) |
申请公布日期 |
2014.07.24 |
| 申请号 |
US201113387714 |
申请日期 |
2011.01.27 |
| 申请人 |
Muralimanohar Naveen;Udipi Aniruddha;Niladrish Chatterjee;Rajeev Balasubramonian;Davis Alan Lynn;Jouppi Norman Paul |
发明人 |
Muralimanohar Naveen;Udipi Aniruddha;Niladrish Chatterjee;Rajeev Balasubramonian;Davis Alan Lynn;Jouppi Norman Paul |
| 分类号 |
G11C7/10;G06F11/10 |
主分类号 |
G11C7/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory, comprising:
a row address register (412) to store a row address corresponding to a row (608) in a memory array (602); a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address; and a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline. |
| 地址 |
Santa Clara CA US |
