| 主权项 |
1. A semiconductor chip, comprising:
a cache comprising a tag array and a data array, said tag array having lower latency than said data array; a first cache request path that flows into said tag array; a second cache request path that flows into said tag array; logic circuity to determine whether a cache request is a data request or a dataless request, and, place said cache request onto said first cache request path if said cache request is a data request, or, place said cache request onto said second cache request path if said cache request is a dataless request. |
