| 摘要 |
<p>A port current control arrangement, constituted of: a current source arranged to generate a reference current or a predetermined value; an on-chip reference resistor, the generated reference current arranged to produce a reference voltage across the on- chip reference resistor; an on-chip sense resistor, a port current arranged to flow through the on-chip sense resistor and produce a sense voltage across the on-chip sense resistor, wherein the resistance of the on-chip sense resistor exhibits a predetermined relationship with the resistance of the first on-chip reference resistor; and a current control circuit, a first input of the current control circuit arranged to receive the produced reference voltage and a second input of the current control circuit arranged to receive the sense voltage, wherein the current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage.</p> |
