| 摘要 |
PROBLEM TO BE SOLVED: To provide multivalued logic means with a synchronization latching function.SOLUTION: A multivalued logic circuit achieving Hooji algebra is configured by: numerical value discrimination means consisting of transistors 1, 2, and 17 and resistors 20 and 21; on/off drive means operating on the basis of a discrimination result signal of the numerical value discrimination means, and consisting of transistors 22-25; and bi-directional pull-switching means consisting of on/off-driven transistors 3 and 5. With respect to a signal communicated between the numerical value discrimination means and the on/off drive means, a D-type flip-flop 127 operating on the basis of a synchronization signal supplied by synchronization signal supply means consisting of synchronization signal generation means 60, a transistor 61, and resistors 26 and 28, is inserted or connected as binary synchronization type flip-flop means. |
