发明名称 Method of addition with multiple operands, corresponding adder and computer program product
摘要 A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits and a correction signal Ri+1 on N bits, on the basis of a binary input number c, an estimation signal Ui and a correction signal Ri on N bits emanating from a previous iteration i. The estimation signal Ui and the correction signal Ri represent a sum of a least two binary numbers in redundant form. The estimation signal Ui+1 and the correction signal Ri+1 represent, in redundant form, the sum of the at least two binary numbers in redundant form and the binary number c. In other words, such a method makes it possible to sum a further binary number with a result represented in a redundant binary form of the type “U/R”, this result resulting from an initialization or a previous summation, and then to generate a result also in a redundant binary form of the type “U/R”. More precisely, method makes it possible to carry out this summation as many times as there are binary numbers to be added.
申请公布号 US8788563(B2) 申请公布日期 2014.07.22
申请号 US200912936337 申请日期 2009.04.02
申请人 SARL Daniel Torno 发明人 Torno Daniel
分类号 G06F7/50 主分类号 G06F7/50
代理机构 Westman, Champlin & Koehler, P.A. 代理人 Brush David D.;Westman, Champlin & Koehler, P.A.
主权项 1. An addition device for adding a plurality of input binary numbers each represented by a digital signal of N bits, wherein the device comprises: inputs configured to receive the digital signals representing the plurality of input binary numbers; at least one accumulation device configured to carry out, each time that it is activated, one iteration, of index i+1 with i≧0, of an accumulation mechanism, each accumulation device comprising estimation means selected from the group consisting of: first estimation means for generating an estimation signal Ui+1 on N bits, and first correction means for generating a first correction signal Ri+1 on N bits, said first estimation means and said first correction means comprising means for implementing the following first set of equations: {Uni+1=Uni⊕Rni⊕Un-1i⊕cnRn+1i+1=(Uni⊕Rni⊕Un-1i)·(Uni⊕cn) and second estimation means for generating an estimation signal Ui+1 on N bits, and second correction means for generating a second correction signal Hi+1 on N bits, said second estimation means and said second correction means comprising means for implementing the following second set of equations: {Uni+1=Uni⊕Hni⊕cnHn+1i+1=(Uni⊕Hni)·(Uni⊕cn_)⊕cnwith:Ui+1n: value of the bit of rank n of said estimation signal Ui+1, with 0≦n≦N−1, obtained during said iteration of index i+1;Uin: a value of the bit of rank n of an estimation signal Ui, obtained during a preceding iteration of index i if i>0, or a determined initialization value U0n of the bit of rank n of an estimation signal Ui if i=0;Uin−1: a value of the bit of rank n−1 of said estimation signal Ui, obtained during a preceding iteration of index i if n>0 and if i>0, or a determined initialization value U0n−1 of the bit of rank n−1 of said estimation signal Ui if n>0 and if i=0; or a predetermined initialization value of an fictive bit of rank n−1 of said estimation signal Ui if n=0;Rin: a value of the bit of rank n of a first correction signal Ri, obtained during a preceding iteration of index i if n>0, or a predetermined initialization value of the bit of rank n of said first correction signal Ri if n=0;Ri+1n+1: a value of the bit of rank n+1 of said first correction signal Ri+1, obtained during said iteration of index i+1;Hin: a value of the bit of rank n of a second correction signal Hi, obtained during a preceding iteration of index i;Hi+1n+1: a value of the bit of rank n+1 of said second correction signal Hi+1, obtained during said iteration of index i+1;Cn: a value of the bit of rank n of an input binary number C included in said plurality of input binary numbers and taken into account in said addition during said iteration of index i+1,the estimation signal Ui and the first correction signal Ri or the second correction signal Hi representing a sum of at least two binary numbers of the plurality of input binary numbers in redundant form, the estimation signal Ui+1 and the first correction signal Ri+1 or the second correction signal Hi+1, representing the sum of said at least two binary numbers in redundant form and of the binary number c, wherein the last iteration of Un is the sum Sn of the bit of rank n.
地址 Orleans FR