发明名称 INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM
摘要 In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.
申请公布号 US2014201445(A1) 申请公布日期 2014.07.17
申请号 US201414161397 申请日期 2014.01.22
申请人 Marvell World Trade Ltd. 发明人 Joshua Eitan;Amit Erez;Chapman Shaul;Jamil Sujat;O'Bleness Frank
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项 1. A method comprising: communicating, by ones of a first plurality of processing cores coupled to a respective one of a first plurality of core interface modules, with the respective core interface module of the first plurality of core interface modules, the first plurality of core interface modules being arranged in a first ring network, ones of the first plurality of core interface modules configured to interface the respective processing core to the first ring network by transmitting data between the respective processing core and the first ring network; communicating, by ones of a second plurality of processing cores coupled to a respective ones of a second plurality of core interface modules, with the respective core interface module of the second plurality of core interface modules, the second plurality of core interface modules being arranged in a second ring network, ones of the second plurality of core interface modules configured to interface the respective processing core to the second ring network by transmitting data between the respective processing core and the second ring network; interfacing, by a global ring network, between the first ring network and the second ring network; receiving, by a first core interface module of the first plurality of core interface modules from a corresponding first processing core of the first plurality of processing cores, a transaction request to read data, a first cache being coupled to the first core interface module; and transmitting, by the first core interface module, the transaction request to a second core interface module of the first plurality of core interface modules to check if the data to be read is cached in a second cache that is coupled to the second core interface module.
地址 St. Michael BB