Communication apparatuses and wireless communications modules

摘要

A communication apparatus having a first and second wireless communications modules is provided. The first wireless communications module includes a receiving unit receiving RF signals from an air interface, a signal processing module performing frequency down conversion on the RF signals to generate baseband signals according to a clock signal, and a processor processing the baseband signals. The processor further detects an ON/OFF status of the second wireless communications module to obtain a detection result and compensates for frequency drift of the clock signal according to the detection result.

主权项

1. A communications apparatus, comprising:
a first wireless communications module, arranged to provide a first wireless communications service and comprising:
a receiving unit, arranged to receive RF signals from an air interface;a signal processing module, arranged to perform frequency down conversion on the RF signals to generate baseband signals according to a clock signal; anda processor, arranged to process the baseband signals; a second wireless communications module, arranged to provide a second wireless communications service; and a clock generating unit, comprising an oscillator for generating the clock signal and a phase-locked loop (PLL) circuit for generating a local oscillating signal according to the clock signal; wherein the processor further detects an ON/OFF status of the second wireless communications module to obtain a detection result, and compensates for frequency drift of the clock signal according to the detection result; wherein the detection result is determined according to an enable signal generated from the second wireless communications module to the processor to indicate the ON/OFF status of the second wireless communications module; and wherein the processor compensates for the frequency drift of the clock signal by adjusting an oscillating frequency of the local oscillating signal via adjusting a divisor of a frequency divider comprised in the PLL circuit according to the detection result or the processor compensates for the frequency drift of the clock signal by adjusting a bandwidth of a loop filter comprised in the PLL circuit according to the detection result.