Branch history with polymorphic indirect branch information

摘要

A system and method for efficient improvement of branch prediction in a microprocessor with negligible impact on die-area, power consumption, and clock cycle period. It is determined if a program counter (PC) register contains a polymorphic indirect unconditional branch (PIUB) instruction. One determination may be searching a table with a portion or all of a PC of past PIUB instructions. If a hit occurs in this table, the global shift register (GSR) is updated by shifting a portion of the branch target address into the GSR, rather than updating the GSR with a taken/not-taken prediction bit. The stored value in the GSR is input into a hashing function along with the PC in order to index prediction tables such as a pattern history table (PHT), a branch target buffer (BTB), an indirect target array, or other. The updated value due to the PIUB instruction improves the accuracy of the prediction tables.

主权项

1. A control flow prediction unit comprising:
a global history shift register (GSR); update logic, wherein in response to determining:
a branch instruction has more than two targets, is indirect, and unconditional, the update logic is configured to derive a value for storage in the GSR based on one or more bits of a branch target address of the branch instruction, wherein said value replaces selected bits of the GSR without performing a shift operation; andthe branch instruction is direct, conditional, or has fewer than three targets, said value comprises a taken/not-taken prediction bit to be shifted into the GSR for the branch instruction.