Microprocessor cache line evict array

摘要

An apparatus for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level memory to a higher-level memory in the hierarchy includes an eviction engine and an array of storage elements. The eviction engine is configured to move the cache line from the lower-level memory to the higher-level memory. The array of storage elements are coupled to the eviction engine. Each storage element is configured to store an indication for a corresponding cache line stored in the lower-level memory. The indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level memory to the higher-level memory.

主权项

1. An apparatus for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level cache memory to a higher-level cache memory in the hierarchy, the apparatus comprising:
an eviction status array, separate accessible from a tag array of the lower-level cache memory; wherein the tag array stores address tags for corresponding cache lines of the lower-level cache memory; wherein the eviction status array comprises an array of storage elements; wherein each of the tag array and eviction status array are accessed by an index portion of memory address; and an eviction engine, configured to move the cache line from the lower-level cache memory to the higher-level cache memory; wherein each storage element of the eviction status array is configured to store an indication for a corresponding cache line stored in the lower-level cache memory, wherein the indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level cache memory to the higher-level cache memory.