发明名称 Physical layer channel synchronization method for high bit-rate cable transmissions
摘要 A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to marry up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.
申请公布号 US8781052(B2) 申请公布日期 2014.07.15
申请号 US201213529366 申请日期 2012.06.21
申请人 Intel Corporation 发明人 Arambepola Bernard;Shulman Shaul;Goldman Naor;Klimker Amos;Tal Noam
分类号 H04J3/06;H04L7/04;H04L7/00 主分类号 H04J3/06
代理机构 Prass LLP 代理人 Ramirez Ellis B.;Prass LLP
主权项 1. A method for synchronizing cable data channels, comprising: receiving a plurality of data packets transmitted over a plurality of data channels at a receiving node, wherein each data packet has a packet header with a continuity counter field; combining the plurality of data packets into groups based on a transmission constellation respective to the data channel in which each data packet is transmitted; segregating each group of the plurality of data packets into subgroups according to same bit counter values identified in the continuity counter field, each subgroup comprising a number of data packets transmitted at a same time over the plurality of data channels and identified as having the same bit counter value; assigning differential delays, with a processor, to each of the number of data packets in a particular subgroup to synchronize data contained in the data packets; and concatenating, with the processor, the data packets with the differential delays assigned at a physical layer level at the receiving node.
地址 Santa Clara CA US