Transmitter output impedance calibration for output rise and fall time equalization and edge rate control

摘要

A method and apparatus to independently adjust the output rise and fall time of a transmitter for the purposes of improving high-speed signaling characteristics and reducing electromagnetic interference (EMI). Also described is an apparatus to provide a high-speed edge-rate control feature. The disclosed method and apparatus for rise and fall time equalization has a closed-loop calibration system that includes an actuation apparatus within the transmitter driver, a sensing means at the output of the transmitter to measure the degree of rise/fall time imbalance, and a calibration state machine operating on the sensor output to devise correction control inputs to the actuator in the transmitter driver to correct the rise/fall time imbalance. Also described is how the actuation apparatus within the transmitter driver can further be used to provide an open-loop edge-rate control feature for the transmitter.

主权项

1. A method of adjusting the rise time and fall time of output signals generated by a voltage-mode differential transmitter (VMT), the method comprising:
a) receiving at least one of a first output signal generated by a first driver of the VMT and a second output signal generated by a second driver of the VMT to obtain at least one received signal, the first driver including first inverter elements electrically connected to each other in parallel, the second driver including second inverter elements electrically connected to each other in parallel, each first inverter element and each second inverter element having a PMOS device and an NMOS device, the first output signal and the second output signal having a rise time and a fall time; b) processing the at least one received signal to determine if there is difference between the fall time and the rise time; and c) responsive to determining that there is a difference between the fall time and the rise time, modifying, in each of the first driver and the second driver, a ratio of a number of enabled PMOS devices to a number of enabled NMOS devices to reduce the difference between the fall time and the rise time.