发明名称 |
Systems and methods for controlled wedge spacing in a storage device |
摘要 |
Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide clock generation systems that include: a first clock multiplier circuit, a second clock multiplier circuit, a modulus accumulator circuit, and a data clock phase control circuit. The first clock multiplier circuit is operable to multiply a reference clock by a first multiplier to yield a first domain clock, and the second clock multiplier circuit is operable to multiply the reference clock by a second multiplier to yield a second domain clock. The modulus accumulator circuit is operable to yield a value indicating a fractional amount of the second domain clock that an edge of the second domain clock is offset from a trigger signal. The data clock phase control circuit is operable to phase shift the second domain clock by a phase amount corresponding to the fractional amount. |
申请公布号 |
US8780476(B2) |
申请公布日期 |
2014.07.15 |
申请号 |
US201113242983 |
申请日期 |
2011.09.23 |
申请人 |
LSI Corporation |
发明人 |
Grundvig Jeffrey P. |
分类号 |
G11B5/09 |
主分类号 |
G11B5/09 |
代理机构 |
Hamilton DeSanctis & Cha |
代理人 |
Hamilton DeSanctis & Cha |
主权项 |
1. A clock generation system, the clock generation system comprising:
a first clock multiplier circuit operable to multiply a reference clock by a first multiplier to yield a first domain clock; a second clock multiplier circuit operable to multiply the reference clock by a second multiplier to yield a second domain clock; a modulus accumulator circuit operable to yield a value indicating a fractional amount of the second domain clock that an edge of the second domain clock is offset from a trigger signal; a data clock phase control circuit operable to phase shift the second domain clock by a phase amount corresponding to the fractional amount; and a rounding and scaling circuit operable to modify the value indicating the fractional amount to conform to a step size implementable by the data clock phase control circuit to yield the phase amount corresponding to the fractional amount. |
地址 |
San Jose CA US |