| 发明名称 | Field-effect transistor, semiconductor wafer, method for producing field-effect transistor and method for producing semiconductor wafer | ||
| 摘要 | Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1≦1, 0≦y1≦1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0≦x2≦1, 0≦y2≦1, y2≠y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer. | ||
| 申请公布号 | US8779471(B2) | 申请公布日期 | 2014.07.15 |
| 申请号 | US201213413216 | 申请日期 | 2012.03.06 |
| 申请人 | Sumitomo Chemical Company, Limited;The University of Tokyo;National Institute of Advanced Industrial Science and Technology | 发明人 | Hata Masahiko;Yamada Hisashi;Fukuhara Noboru;Takagi Shinichi;Takenaka Mitsuru;Yokoyama Masafumi;Yasuda Tetsuji;Urabe Yuji;Miyata Noriyuki;Itatani Taro;Ishii Hiroyuki |
| 分类号 | H01L29/66 | 主分类号 | H01L29/66 |
| 代理机构 | Sughrue Mion, PLLC | 代理人 | Sughrue Mion, PLLC |
| 主权项 | 1. A field-effect transistor comprising: a gate insulating layer; a first semiconductor crystal layer in contact with the gate insulating layer; a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer, the second semiconductor crystal layer being in contact with a source electrode and a drain electrode, and the source electrode and the drain electrode being in contact with only the second semiconductor crystal layer; and a third semiconductor crystal layer lattice-matching or pseudo lattice-matching the second semiconductor crystal layer, wherein the third semiconductor crystal layer is positioned between the first semiconductor crystal layer and the second semiconductor crystal layer, wherein the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1≦1, 0≦y1≦1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0≦x2≦1, 0≦y2≦1, y2≠y1), the third semiconductor crystal layer is made of Alx3Inx4Ga1-x3-x4Asy3P1-y3 (0<x3<1, 0≦x4<1, 0<x3+x4<1, 0≦y3≦1), the electron affinity Ea3 of the third semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer, and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer. | ||
| 地址 | Tokyo JP | ||