发明名称 Logic circuit
摘要 A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.
申请公布号 US8779799(B2) 申请公布日期 2014.07.15
申请号 US201213467500 申请日期 2012.05.09
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Takewaki Yoshiya
分类号 H03K19/20;G11C11/34 主分类号 H03K19/20
代理机构 Robinson Intellectual Property Law Office, P.C. 代理人 Robinson Eric J.;Robinson Intellectual Property Law Office, P.C.
主权项 1. A logic circuit comprising: first to fourth transistors; fifth to eighth transistors; a ninth transistor and a tenth transistor with gates electrically connected to each other; and an eleventh transistor with one of a source and a drain electrically connected to the gates of the ninth transistor and the tenth transistor, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the eighth transistor, wherein a gate of the first transistor, a gate of the third transistor, and a gate of the eighth transistor are electrically connected to each other. wherein a gate of the second transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected to each other, wherein a gate of the sixth transistor, a gate of the seventh transistor, the gate of the ninth transistor, and the gate of the tenth transistor are electrically connected to the one of the source and the drain of the eleventh transistor, where a node is formed, wherein one of a source and a drain of the ninth transistor is electrically connected to the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor, wherein the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the fifth transistor and one of a source and a drain of the sixth transistor, wherein one of a source and a drain of the tenth transistor is electrically connected to one of a source and a drain of the third transistor and the other of the source and the drain of the fourth transistor, wherein the other of the source and the drain of the tenth transistor is electrically connected to one of a source and a drain of the seventh transistor and the other of the source and the drain of the eighth transistor, wherein the other of the source and the drain of the second transistor, the other of the source and the drain of the third transistor, the other of the source and the drain of the sixth transistor, and the other of the source and the drain of the seventh transistor are electrically connected to each other, and wherein the eleventh transistor includes an oxide semiconductor.
地址 Atsugi-shi, Kanagawa-ken JP