摘要 |
<p>PROBLEM TO BE SOLVED: To reduce power consumption in a wide I/O region in a semiconductor integrated circuit having a plurality of TSV bumps which are arranged in arrays.SOLUTION: In a semiconductor integrated circuit, two ESD protection elements connected to two TSV bumps are arranged between the two TSV bumps every four TSV bumps arranged two by two in series lengthwise and widthwise. Further, separating polarities of the ESD protection elements in a lengthwise direction and a widthwise direction of the arrangement achieves efficient wiring in connection with a power source trunk line, and reducing the size of the ESD protection elements decreases parasitic capacitance occurring between sources and drains of the ESD protection elements and a silicon substrate, reduces a leakage current and saves power consumption in a wide I/O region.</p> |