发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To reduce power consumption in a wide I/O region in a semiconductor integrated circuit having a plurality of TSV bumps which are arranged in arrays.SOLUTION: In a semiconductor integrated circuit, two ESD protection elements connected to two TSV bumps are arranged between the two TSV bumps every four TSV bumps arranged two by two in series lengthwise and widthwise. Further, separating polarities of the ESD protection elements in a lengthwise direction and a widthwise direction of the arrangement achieves efficient wiring in connection with a power source trunk line, and reducing the size of the ESD protection elements decreases parasitic capacitance occurring between sources and drains of the ESD protection elements and a silicon substrate, reduces a leakage current and saves power consumption in a wide I/O region.</p>
申请公布号 JP2014131007(A) 申请公布日期 2014.07.10
申请号 JP20130218410 申请日期 2013.10.21
申请人 RENESAS ELECTRONICS CORP 发明人 ISHIKAWA KENICHI
分类号 H01L21/822;H01L21/3205;H01L21/768;H01L21/82;H01L23/522;H01L27/04 主分类号 H01L21/822
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