Semiconductor device having complementary bit line pair

摘要

Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively.

主权项

1. A device comprising:
first and second bit lines; a first dummy cell coupled to the first bit line; a second dummy cell coupled to the second bit line; a sense amplifier coupled between the first and second bit lines and configured to drive, when activated, the first bit line to one of first and second voltages such that a voltage of the first dummy cell becomes one of the first and second voltages and drive, when activated, the second bit line to the other of the first and second voltages such that a voltage of the second dummy cell becomes the other of the first and second voltages; an equalizing circuit coupled between the first and second bit lines and configured to short-circuit, when activated, the first and second bit lines so as to change the voltage of the first dummy cell from the one of the first and second voltages to a third voltage and the voltage of the second dummy cell from the other of the first and second voltages to the third voltage, the third voltage being between the first and second voltages; and a first memory cell coupled to the first bit line and configured to store a first data, wherein the sense amplifier is configured to drive the first and second bit lines in response to the first data, and wherein the first memory cell and the second dummy cell are connected respectively to the first and second bit lines while the first dummy cell is disconnected from the first bit line in a first period of time, and the first and second dummy cells are connected respectively to the first and second bit lines while the first memory cell is disconnected from the first bit line in a second period of time that follows the first period of time.