Failure analysis using design rules

摘要

The use of design rule checks for failure analysis of semiconductor chips is described. The smaller geometries of recent semiconductor devices lead to a much higher level of sensitivity of devices to photolithography related systematic problems. Failure analysis to date has focused on physical, randomly distributed defects of devices rather than systematic problems caused by the mask manufacturing or mask application process. Methods and systems are described which allow for online searches of a layout database for geometric features defined by a set of rules. The rules may be defined as two-dimensional Boolean operations including shape or distance based as well as any kind of combination. The result is graphically and interactively presented.

主权项

1. A computer implemented method for performing semiconductor analysis comprising:
performing semiconductor failure analysis comprising:
importing a semiconductor layout and a netlist corresponding to the semiconductor layout;having a set of rules wherein each rule of the set of rules describes a design rule check for the semiconductor layout;selecting a rule from the set of rules to apply to the semiconductor layout wherein the rule describes a two-dimensional Boolean operation on shapes where the rule further describes the shapes of one or more layers;identifying a portion of the semiconductor layout by searching through the semiconductor layout for a match to the rule which was selected;performing electrical analysis on the netlist where the rule further describes shapes of waveforms resulting from the electrical analysis; anddisplaying the portion of the semiconductor layout.