Method and architecture for pre-bond probing of TSVs in 3D stacked integrated circuits

摘要

On-chip test architecture and design-for-testability methods for pre-bond testing of TSVs are provided. In accordance with certain embodiments of the invention, a die level wrapper is provided including gated scan flops connected to one end of each TSV. The gated scan flops include a scan flop structure and a gated output. The gated output is controlled by a signal to cause the output of the gated scan flop to either be in a “floated state” or take the value stored in the flip-flop portion of the gated scan flop. The gated output of the gated scan flop can be used to enable resistance and capacitance measurements of pre-bonded TSVs.

主权项

1. An on-chip architecture for through-silicon-via (TSV) testing, comprising:
a scan flop receiving a clock signal input, a test input, a functional input, and a test select input; and providing a first signal at an output node; and an open signal controlled gate element at the output node of the scan flop, the gate element receiving the first signal from the scan flop and providing a Q output to a TSV, wherein the gate element receives the open signal to control whether the Q output is floating or takes a value of the first signal.