Generation of a replay module for simulation of a circuit design

摘要

Approaches are disclosed for testing a module of a circuit design. The module is simulated a first time using a testbench on a programmed processor. Event data is captured to a first file during the simulating. For each event, the event data describes a signal identifier, an associated signal value, and an associated timestamp. The event data of the first file is transformed into a hardware description language (HDL) replay module.

主权项

1. A method of testing a module of a circuit design, comprising:
simulating the module a first time using a testbench on a programmed processor; capturing event data to a first file during the simulating, for each event the event data describing a signal identifier, an associated signal value, and an associated timestamp; and transforming the event data of the first file into a hardware description language (HDL) replay module that drives input signals to the module of the circuit design, wherein the transforming includes the programmed processor:
selecting data from the first file for translation into the replay module;writing HDL statements that recreate port transition events of the first file in the replay module; andinserting delay statements into the replay module for retaining timing of events of the first file.