发明名称 RGB-out dither interface
摘要 A display controller may include an RGB Interface module and a display port module, which may both use a target-master interface, in which the data receiving module pops pixels from the data sourcing module, and generates the HSync, VSync, and VBI timing signals. A dither module may be instantiated between the RGB interface module and display port module to perform dithering. The dither module may use a source-master interface, in which data signals and data valid signals are issued by the data sourcing module. In order to avoid having to use a large storage capacity FIFO with the dither module, a control unit may issue interface signals to the RGB Interface module and display port module, and clock-gate the dither module, to allow the data signals and data valid signals to properly interface with the RBG interface module and display port module, and provide data flow from the RGB interface module to the dither module to the display port module.
申请公布号 US8773455(B2) 申请公布日期 2014.07.08
申请号 US201113207805 申请日期 2011.08.11
申请人 Apple Inc. 发明人 Tripathi Brijesh;Bhargava Nitin
分类号 G09G5/00;G09G5/02;G09G1/28;G06F13/14;G06T15/00;G09G5/10;H04N9/44;H04N11/00;H03M1/12;H04N9/12;G06F5/00;G06F15/00;G09G5/395;G06F13/24;G06F15/76;G06F9/40;G06F9/00;G09G5/18;G09G3/20 主分类号 G09G5/00
代理机构 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. 代理人 Merkel Lawrence J.;Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
主权项 1. An apparatus comprising: a display controller interface module having a target-master interface, the display controller interface module configured to output a pixel stream of pixel values; a dither module having a source-master interface, the dither module coupled to receive the pixel stream from the display controller interface module, and configured to dither the pixel values of the received pixel stream to obtain a dithered pixel stream; a display port module having a target-master interface, the display port module coupled to receive pixels of the dithered pixel stream, and configured to transmit the received pixels of the dithered pixel stream; and a control unit configured to generate interface signals to the display controller interface module and the dither module, and clock-gate the dither module, to manage flow of the pixel stream from the display controller interface module to the dither module to the display port module.
地址 Cupertino CA US