CONVERSION CIRCUITRY FOR REDUCING PIXEL ARRAY READOUT TIME

摘要

An image sensor includes a pixel array having pixels arranged in rows and columns, a first successive-approximation-register (“SAR”) analog-to-digital-converter (“ADC”), a second SAR ADC, and first and second control circuitry. The first SAR ADC includes a first capacitor array (“FCA”) that shares a first common terminal coupled to a first comparator and coupled to receive first analog pixel signals. The second SAR ADC includes a second capacitor array (“SCA”) that shares a second common terminal selectably coupled to a second comparator and coupled to receive second analog pixel signals. The first and second control modules are coupled to selectably switch bottom plates of the FCA from a low reference voltage to the high reference voltage at a same time as selectably switching bottom plates of the SCA from a high reference voltage to the low reference voltage.

主权项

1. An image sensor comprising:
a pixel array having pixels arranged in rows and columns; a first successive-approximation-register (“SAR”) analog-to-digital-converter (“ADC”) coupled to convert a first analog pixel signal to first digital data, the first SAR ADC including a first capacitor array (“FCA”) with binary-weighted values, wherein top plates of the FCA share a first common terminal coupled to a first comparator input and bottom plates of the FCA are coupled to switch from a low reference voltage to a high reference voltage, and wherein the first common terminal is selectably coupled to receive the first analog pixel signal generated by a first column of the pixel array; a second SAR ADC coupled to convert a second analog pixel signal to second digital data, the second SAR ADC including a second capacitor array (“SCA”) with binary-weighted values, wherein top plates of the SCA share a second common terminal coupled to a second comparator input and bottom plates of the SCA are coupled to switch from the high reference voltage to the low reference voltage, and wherein the second common terminal is selectably coupled to an inverter output of an inverter that inverts the second analog pixel signal generated by a second column of the pixel array; and first control circuitry of the first SAR ADC coupled to selectably switch the bottom plates of the FCA from the low reference voltage to the high reference voltage in response to control signals at substantially a same time as second control circuitry of the second SAR ADC selectably switches the bottom plates of the SCA from the high reference voltage to the low reference voltage in response to the control signals.