A/D CONVERSION CIRCUIT AND SOLID-STATE IMAGING DEVICE

摘要

In an A/D conversion circuit and a solid-state imaging device, a latch circuit is in a disable state until a first timing at which an output signal of a comparison unit has been inverted, and is in an enable state until a second timing at which a delay time of the inversion delay circuit has passed from the first timing. The latch circuit is in the enable state until the second timing according to comparison start in the comparison unit. The latch circuit latches an output signal of a delay unit at the second timing. A determination unit determines whether the latch circuit accurately latches the output signal of the delay unit, and outputs a signal indicating a determination result to a delay controller. The delay controller controls the delay time of the inversion delay circuit based on the determination result.

主权项

1. An A/D conversion circuit comprising:
a comparison unit configured to receive an analog signal and a reference signal that increases or decreases with lapse of time, to compare the analog signal with the reference signal, and to output a first comparison signal at a first timing at which the analog signal and the reference signal have a predetermined relation; a signal generation unit configured to output a second comparison signal, a logic state of which changes, at a second timing at which a predetermined time has lapsed from the first timing, and to output a third comparison signal, a logic state of which changes, at the first timing and the second timing based on a result obtained by performing a logic operation on the first comparison signal and the second comparison signal; a clock generation unit configured to output n clock signals from a first clock signal to an n-th (where n is a natural number greater than or equal to 2) clock signal, which have different phases from each other, a latch unit that includes n latch units from a first latch unit to an n-th latch unit, each latch unit having a first input terminal to which a corresponding one of the n clock signals from the first clock signal to the n-th clock signal is input, a second input terminal to which a control signal entering a first logic state corresponding to a valid state of a latch unit and a second logic state corresponding to an invalid state of a latch unit is input based on the second comparison signal or the third comparison signal, and an output terminal; a counter configured to perform counting based on a signal from the one output terminal of k latch units from an (n−k+1)th (where k is a natural number greater than or equal to 1 and smaller than or equal to n−1) latch unit to the n-th latch unit; a determination unit configured to determine a logic state of the clock signal latched in the latch unit based on at least one of signals from the output terminals of (n−k) latch units from the first latch unit to an (n−k)th latch unit, and to output a determination signal; and a time controller configured to control a length of the predetermined time based on the determination signal, wherein the control signal, which is input to the (n−k) latch units from the first latch unit to the (n−k)th latch unit, is in the second logic state from a timing according to comparison start in the comparison unit to the first timing based on the third comparison signal, and is in the first logic state from the first timing to the second timing based on the third comparison signal, a control signal, which is input to the k latch units from the (n−k+1)th latch unit to the n-th latch unit, is in the first logic state from the timing according to the comparison start in the comparison unit to the second timing based on the second comparison signal, and the n latch units from the first latch unit to the n-th latch unit latch logic states of the n clock signals at the second timing.