| 摘要 |
A solid state imaging device 1 includes a photodetecting section 10, a signal readout section 20, a controlling section 30, dummy photodetecting sections 11 and 12 including dummy photodiodes, discharging arrangement for discharging junction capacitance portions of the dummy photodiodes, and a scintillator layer 50 provided so as to cover the photodetecting section 10. The dummy photodetecting section 11 is disposed so as to neighbor the first row (the upper side of the photodetecting section 10) of the photodetecting section 10 and has a length equivalent to the length of the photodetecting section 10 in the left-right direction. The dummy photodetecting section 12 is disposed so as to neighbor the M-th column of the photodetecting section 10 (the lower side of the photodetecting section 10) and has a length equivalent to the length of the photodetecting section 10 in the left-right direction. |
| 主权项 |
1. A solid state imaging device comprising:
a photodetecting section including M×N pixel portions P1,1 to PM,N two-dimensionally arrayed in M rows and N columns, each including a photodiode which generates charges as much as incident light intensity and a switch connected to the photodiode, where the photodiode is connected to a readout wiring LO,n via the switch in each pixel portion Pm,n; a scintillator layer which is provided so as to cover the photodetecting section and generates scintillation light in response to incidence of radiation; a dummy photodetecting section including dummy photodiodes disposed so as to neighbor the outer sides of the first row and the M-th row of the photodetecting section; a signal readout section which is provided on the outer side of the first row or the M-th row of the photodetecting section, includes N integrating circuits S1 to SN and N holding circuits H1 to HN, accumulates charges input into each integrating circuit Sn through the readout wiring LO,n in a capacitive element and outputs a voltage value corresponding to the accumulated charge amount, and holds the voltage value output from the integrating circuit Sn in each holding circuit Hn and outputs the voltage value; and a bias voltage supply wiring connected to the dummy photodiodes, wherein the bias voltage supply wiring discharges the junction capacitance portion of the dummy photodiodes by applying a fixed voltage to the dummy photodiodes, where M and N are integers not less than 2, M<N, m is an integer not less than 1 and not more than M, and n is an integer not less than 1 and not more than N, wherein the photodetecting section, the dummy photodetecting section, and the signal readout section are formed on a same semiconductor substrate, and wherein a peripheral region other than the photodetecting section of the semiconductor substrate is larger than an area formed by the photodetection section. |
