Synthesis flow for formal verification

摘要

Processing a circuit design includes generating a transformation output from a transformation input for each of a plurality of transformations of a synthesis flow applied to the circuit design. For each transformation, the transformation input and the transformation output represent the circuit design. At least one circuit element is changed from the transformation input to the transformation output. For each transformation, a hardware description language representation of the transformation input and a hardware description language representation of the transformation output are generated. For each transformation, determining whether the hardware description language representation of the transformation input is equivalent to the hardware description language representation of the transformation output.

主权项

1. A method of processing a circuit design, comprising:
generating, using a processor, a transformation output from a transformation input for each of a plurality of transformations of a synthesis flow applied to the circuit design; wherein, for each transformation, the transformation input and the transformation output represent the circuit design and at least one circuit element is changed from the transformation input to the transformation output; for each transformation, generating a hardware description language representation of the transformation input and a hardware description language representation of the transformation output; and for each transformation, determining whether the hardware description language representation of the transformation input is equivalent to the hardware description language representation of the transformation output.