Current-mode buffer with output swing detector for high frequency clock interconnect

摘要

A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.

主权项

1. A current-mode driver circuit comprising:
a first PMOS transistor having a gate terminal receiving an oscillating signal and a source terminal receiving a first supply voltage; a first NMOS transistor having a gate terminal receiving the oscillating signal and a source terminal receiving a second supply voltage; a first variable conductivity circuit having a first input terminal coupled to a drain terminal of the first PMOS transistor and an output terminal coupled to a common node; a second variable conductivity circuit having a first input terminal coupled to a drain terminal of the first NMOS transistor, said second variable conductivity circuit having an output terminal coupled to the common node; and a control circuit adapted to increase conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, said control circuit further adapted to decrease the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node, and wherein the control circuit comprises a first biasing circuit, said first biasing circuit comprising: a first current mirror; a first capacitor; and a first differential amplifier comprising a second NMOS transistor having a source terminal responsive to the voltage of the common node.