Device and method for a multiplexor/demultiplexor reset scheme

摘要

Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset state. A clock source provides an ungated common clock signal. A clock gating circuit generates the gated common clock signal based on the ungated common clock signal, and is configured to hold the gated common clock signal while the asynchronous reset signal is asserted. The clock gating circuit provides the gated common clock signal to the dividers when the asynchronous reset signal is de-asserted.

主权项

1. A circuit comprising:
a chain of one or more cascading units, wherein each cascading unit receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams; a chain of one or more dividers coupled to said chain of one or more cascading units for providing one or more divided clock signals to said chain of one or more cascading units, wherein said one or more divided clock signals is based on a gated common clock signal; an asynchronous reset signal delivered to said chain of one or more dividers, and when asserted sets said chain of one or more dividers to a reset state, wherein said asynchronous reset signal propagates through said chain or one or more dividers from a downstream side; a clock source providing an ungated common clock signal; a clock gating circuit configured for generating said gated common clock signal based on said ungated common clock signal, and configured to hold said gated common clock signal while said asynchronous reset signal is asserted, wherein said clock gating circuit is configured to provide said gated common clock signal to said chain of one or more dividers when said asynchronous reset signal is de-asserted; a retiming circuit configured to receive said ungated common clock signal and said reset asynchronous reset signal, wherein said retiming circuit generates a retimed reset signal that is de-asserted such that the gated common clock signal starts up undistorted after being released from reset.