| 摘要 |
An address input circuit comprises a first address input unit which generates a first internal address at the time of inputting an active command by latching a first address which is inputted to a first pad; and a second address input unit which generates a second internal address at the time of inputting the active command by delaying the first address which is inputted to the first pad when entering a test mode and generates the second internal address at the time of inputting the active command by latching a second address which is inputted to a second pad when not in the test mode. |
